A Simulation Model for Power VDMOS

A sub-circuit model is proposed for the power VDMOS device by using the parasitic resistors RS/RD/RG/RDS and the parasitic diode D based on the MOSFET model in this paper. It should be noted that RD is not a fixed resistance, but a variable resistance controlled by the gate voltage and the drain voltage to improve the accuracy of the spice model. This model is well verified by the TCAD simulation data.