The Multi-input MRL Logic Gate and Its Application

This paper discusses the design constraints on the multi-input Memristor Ratioed Logic (MRL) AND and OR gates, and it is found out that the number of inputs is limited by the resistance ratio between the high resistance and low resistance values. A design case of a 4-1 multiplexer with the multi-input MRL gates is presented. The simulation results show that it has a smaller area and higher speed compared with that of the counterpart with the two-input MRL gates.