Adopting High-level Synthesis Approach to Accelerate Power Management Design

High-level synthesis (HLS) is rapidly gaining its position in hardware design. With nowadays designs complexity and continuously growing pressure to cut down the time-to-market it is now inevitable to raise the hardware design from Register-Transfer Level (RTL) to the higher-level of abstraction, commonly known as Electronic System Level (ESL). The HLS naturally brings an increase in design productivity and by adopting current techniques like IP reuse and formal verification the design correctness could be improved as well. However, the available studies show that the recent HLS tools still have a lot of limitations. Not only the design quality could be improved, concerning for example performance or energy-efficiency, but also various design techniques, currently applied at RTL and lower levels, should be supported at the ESL. The low power design techniques belong to the group. Application of these techniques is especially important in fault-tolerant systems, where an incorporated overhead results in highly increased power consumption. Although low power design is supported by standard RTL specification it is still significantly challenging, as well as highly error prone work, to apply these techniques to the HLS synthesized design. We present an approach to ESL power intent specification, together with the proposed HLS methods for generating an equivalent standard RTL specification of power management. The approach substantially reduces the power management specification and provides for rapid RTL-precise power estimation, offering thus the fast exploration of various power architectures. What is more, our current research aims for automated ESL power intent generation that could make the adoption of low power design techniques fully transparent.