Low Noise L band PLL-VCO designed for the IRNSS -Rx using BiCMOS 180 nm Process

A Low Noise L band PLL-VCO designed for the IRNSS-Rx using Sbc18h2 180 nm BiCMOS SiGe 180 nm Process. A SiGe HBT (heterojunction bipolar transistor) BiCMOS process have been used for the very low noise VCO design. NPN transistors based cross coupled architecture have been used for the low noise VCO design. Complete PLL integration with VCO have been designed and tested. Very good phase noise has been achieved from the BiCMOS based VCO. PLL is successfully locked and working. The designed BiCMOS PLL is not only giving the better phase noise performance but also better spurious rejection in the locked condition have been achieved.