Surface-modification technology by using Radical Shower Treatment (RST) process in submicron interposer for Fan-out packaging applications

In recent years, discussion on power consumption and latency of GPU used for AI application has started. In order to realize further high-speed processing and low power consumption of the GPU processing a huge amount of data, it is necessary to consider the packaging structure of the GPU [1]. The current GPU package structure is based on the package substrate using flip chip PoP (Package on Package) technology and Si interposer. In this structure applied, the wiring distance is increased due to the structural restriction of signal transmission through the Si interposer on the package substrate, which is the cause of the increase in power consumption and latency. Therefore, the packaging structure around the Si interposer has been focused, and expected structures that does not use the Si interposer have been proposed [2]. A method of directly forming fine wiring layers which plays a role of RDL (Redistributed Layer) by using a photosensitive insulation material on a build-up substrate without using a Si interposer has been reported [3]. Furthermore, in view of the high frequency trend of the signal frequency, the development of glass-epoxy materials having low Df (dielectric loss constant) and low D
k
(dielectric constant) material properties as a build-up film is proceeding [4]. It is expected that it will be a more effective method to effectively utilize the characteristics of low D
f
and low D
k
and to form fine wiring on the build-up layer using semiconductor fine wiring technology. For future high density packaging, plasma dry etching technology aiming fabrication of multilayer wiring on build-up film has been developed [5].In this paper, the results of microfabrication of build-up thickness of 5 μm are reported for the purpose of fabricating fine wiring on build-up film using dry process. This technology has been developed as one of new SiP (System in Package) technologies for realizing future heterogeneous integration. The process results of dry etching and Cu electroplating are described. In order to adapt to chip mounting, the size of the wiring formed in the build-up layer is targeted at line / space = 2 μm / 2 μm. The reason for using Si substrate instead of mold panel is because it is suitable for use of expensive NGD (known good die). In Si semiconductor packaging, very stable technology corresponding to Si substrate of 300 mm size has been established up to today. And, for Cu fine wiring formation on a build-up film using a dry process, it is also necessary to ensure sufficient adhesion between the Cu seed layer and the build-up film. In order to manufacture highly reliable fine Cu wiring, it is necessary to evaluate the controllability of good adhesion of the seed Cu layer / glass epoxy film interface. Fluorine compound gas is used for dry etching of build-up film. There are residues containing fluorine on the surface to be etched. These residual fluorine compounds reduce the adhesion between the build-up film and the seed layer for Cu plating. Therefore, it is necessary to construct a method of dry process to improve the adhesion to the seed layer by eliminating the effect of residual fluorine compound. The change in the surface free energy before the seed sputtering process is compared with the peel test result of the Cu seed layer. Basic investigation results on the surface condition of the build-up film and the adhesion of the seed film are reported.