Design-Technology Co-optimization (DTCO) for Emerging Disruptive Logic & Embedded Memory Process Technologies

In this paper, we discuss the DTCO of two disruptive emerging device technologies; Vertical gate-all-around FETs and embedded monolithic 3D (ITIR) integration of 2D material-based resistive RAM and switch transistors. We showed that VFET has the potential for lower parasitics and improved SRAM performance. In the case of the 2D material-based ITIR, we show that stacking of nanosheets and reduction of set current is necessary to scale the cell below 0.1 μm
²
cell sizes.