A circuit model for evaluating plasma-induced charging damage in bulk and SOI technologies

We describe a circuit-based model of charging damage, in which the plasma characteristics are modeled with simple plasma equations, and devices on the wafer are modeled with standard FET compact models. A circuit solver is then used to determine the nodal potentials and currents. We first use this approach for bulk technology and illustrate some aspects of the model, examining oxide thicknesses of 2.3 nm, 3.5 nm, and 6.8 nm. We then apply the model to understand charging in an SOI technology, where the interconnections may be quite complex and all nodes are independent of the wafer substrate. Although SOI circuits are generally immune to charging damage, some bulk-like behavior may be induced by introducing differential electron shading. Results from the model are compared with data, and then the usefulness of the model in analyzing complex circuits is described.