An Efficient Clock Tree Synthesis Method with Manual Hierachical Operation

A manual hierarchical operation based method for clock tree synthesis is described in this paper. The implementation of this method is adopted in a communication chip design in a 0.13μm CMOS. Comparing with the conventional clock tree synthesis, the manual method can obtain the following achievements: the clock cell area decreased by 19%, hold time violations decreased by 37%, and the number of hold time violations decreased by 45%, and the clock skew was reduced by 20%.