The Rip-up and Reroute Technique Research for Island-Style Reconfigurable System-on-Chip

In this paper several ways to implement the rip-up and reroute technique for reconfigurable system-on-chip (RSoC) interconnect routing were proposed and investigated. The considered RSoC is a new architecture VLSI containing FPGA based reconfigurable logic blocks and IP cores such as RAM, PLL, LVDS, multipliers and others. In our RSoC design flow we used the algorithm for a circuit routing based on the algorithm A*. This is the advanced modification of a classical algorithm of searching the shortest path on a graph, Dijkstra's algorithm. The rip-up and reroute technique is a combinatorial task of sorting and ordering nets array by changing interconnect priority to find the routability solution. Here an attempt has been made to determine the limits of applicability and estimation of the overall efficiency of some simple tricks for a rip-up and reroute technique. Some advantages, limitations, problems and features of each of them are reviewed and discussed.