A 14.3pW Sub-Threshold 2T Gain-Cell eDRAM for Ultra-Low Power IoT Applications in 28nm FD-SOI

Internet of Things (IoT) applications, such as biomedical sensing, often require on-chip embedded memories, which dominate both the silicon area and power of these applications [1, 2]. To adhere to the ultra-low power (ULP) requirements of IoT applications, supply voltage (V
_DD
) scaling down to the sub-threshold voltage (V
_T
) region can be used to significantly reduce both the static and dynamic power consumption of these applications. However, embedded memories, typically implemented with 6T SRAM macros, suffer from decreased noise margins and become unreliable at near V
_T
supply voltages [2-4].