Reduced-Code Static Linearity Test of Split-Capacitor SAR ADCs Using an Embedded Incremental $\Sigma\Delta$ Converter

Reduced-code techniques for an analog-to-digital converter (ADC) static linearity test have the potential to drastically reduce the number of necessary measurements for a complete static linearity characterization. These techniques take advantage of the repetitive operation of certain families of converters such as pipelines, successive-approximation registers (SARs), cyclic, etc. In this paper, we present a novel reduced-code technique for the static linearity test of split-capacitor SAR ADCs based on the on-chip generation and measurement of the major carrier transitions of the input digital-to-analog converter of the converter. The proposed test method does not require a test stimulus, and we show that the necessary measurements can be easily extracted by reconfiguring portions of the SAR into a low-resolution incremental ΣΔ converter. The proposed technique is validated with both behavioral and electrical simulations of a 10-bit SAR ADC in a 65-nm CMOS technology.