A 16KByte SRAM Memory Containing Peripheral Circuit Hardened

A hardened SRAM Memory of 16KByte is completed by the process of SMIC 0.18μm in this paper. The hardened methods used in the SRAM are determined according to the SEU (Single Event Upsets), SEL (Single Event Lock) effect and TID(Total Ionizing Dose) effect. The structure of memory adopts the method of block design, and DICE unit is selected as the memory array. Then, the peripheral circuit of memory is designed, including row and column decoding circuit, data input/output circuit, sensitive amplifier and clock circuit. Simulation results show that the SRAM memory frequency can reach 100MHz, and the access time is about 2.494ns and the power consumption is 19.26mW.