Impact of Gate Asymmetry on Gate-All-Around Silicon Nanowire Transistor Parasitic Capacitance

In this paper, an analytical model is developed for parasitic gate capacitance of the gate-all-around (GAA) silicon nanowire MOSFETs (SNWT) with asymmetrical top and bottom gates. The modeling results show that the gate-to-source/drain spacer significantly impacts on the parasitic capacitance especially in the case of top-to-bottom gate misalignment. It is found that the optimized top-to-bottom gate misalignment may achieve smaller C
_p
/C
_total
so as to improve the AC performance of GAA SNWT. The developed capacitance model is more suitable for the actual process for further device design optimization.