A 1.2V 4bit 25dB SNDR Flash ADC with Configurable Output for GNSS Receiver

A 1.2V 4bit 62MHz Flash ADC analog to digital converter (ADC) for global navigation satellite system (GNSS) receiver is implemented. The ADC can be configured to binary output code, Gray code and thermometer code by serial peripheral interface (SPI) to satisfy different system interface need. The output codes also can be configured to a rising or falling edge in working with baseband chip in actual application. The pre-amplifier in comparator is used to provide appropriate gain and lower the kick-back noise. The input buffer is used to drive the ADC to lower the mutual distortion between programmable gain amplifier (PGA) and ADC. Besides, the comparator's bias current could be minimized by SPI in order to save the static power. The digital bubble circuit can be used to avoid the metal bubble error. The design was fabricated in a 0.13μm CMOS process with an area of 0.12 mm
²
and a total power of 1.0mW. The measurement results show that DNL and INL of the proposed ADC can get ±0.25LSB and +0.25/-0.35LSB. The spurious free dynamic range and signal-to-noise distortion ratio can get 37.5-dB and 25dB, respectively.