ESD and Latch-up failures through triple-well in a 65nm CMOS technology

ESD and latch-up failures in a 65nm CMOS technology are presented where the triggering of a parasitic thyristor occurs despite the triple-well isolation that prevents the formation of a classical 4-layer SCR structure. The influence on triggering of the anode-to-cathode spacing, guard-ring protection and well resistances are studied for this type of parasitic device.