Evaluation of Thermal Stability of Spin-Transfer Torque based Magnoresistive Random-Access Memory for Cache Applications in Advanced Technology Nodes

Modern computing systems require enhanced performance; however, the conventional memories such as Static Random Access Memory (SRAM) are inadequate to support this demand. This is mainly due to the fact that SRAM density cannot be increased commensurately with Complementary Metal-Oxide–Semiconductor (CMOS) transistor scaling. For example, typically the six-transistor (6T) SRAM, which has long been the workhorse of high-performance caches, requires a cell size of $120-200\mathrm {F} _{,}^{2}$ where F is the feature size [1]. On the other hand, Spin-Transfer Torque based Magnetoresistive Random-Access Memory (STT-MRAM) have emerged as universal memory technology due to its non-volatility, endurance, low operating voltages and ultrafast switching [2]. Further, they occupy much less area with 1T design comparable to DRAM with cell size of $6- 10 \mathrm {F}^{2}$ [1]. Thus, STT-MRAM is most suited for on-chip cache applications with highest possible density. One of the most important factors that determines the data retention time of STT-MRAM towards cache applications is the thermal stability of magnetization. It is known that with shrinking Magnetic Tunnel Junction (MTJ) dimensions, commensurate with CMOS scaling, the thermal stability of magnetization also decreases. This results in reduced retention times and increased bit error rates, posing significant challenges towards its application as cache memory. Hence, it is important to evaluate the thermal stability of magnetization as a function of decreasing MTJ diameter, to address their scalability and performance in advanced cache technology. In this article, we focus on perpendicular-MTJ and perform Micromagnetic simulations to evaluate the thermal stability factor at reduced MTJ diameter. Currently, the 22 nm nodes uses MTJ with 55–75 nm diameters [3]. First, we discuss the thermal energy barrier E
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necessary for 7/21 days of data retention for L3-cache applications at different failure in time (FIT) rates. The requirement for the thermal energy barrier is given by: $\mathrm {E}_{b}=- ln[- ( \mathrm {t}_{0}/ \mathrm {t}_{p}) * ln(1 -$FIT$/ \mathrm {N}_{b})]$, where, FIT is failure in time, N
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are no. of bits, $\mathrm {t}_{0}$ is the attempt frequency (assumed to be 1ns) and $\mathrm {t}_{p}$ is desired data retention time span (7/21 days). Figure 1 shows the calculated thermal energy barrier at different FIT's and data retention spans for various sizes of cache memories ranging between 1MB to 1GB. From this Figure, it is evident that the minimum thermal energy barrier should be greater than 20 KT for 1000 FIT's and 27 KT for 0.1 FIT's. Next, we calculate the thermal energy barrier of p-MTJ device to assess whether these demands can be satisfied with shrinking MTJ diameters. For this purpose, we use standard MTJ stack consisting of CoFeB as free layer with 0.85 nm thickness and its diameter varying between 5 – 60 nm to understand the scalability aspect. We perform E
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calculations using a monodomain and domain wall assisted switching mechanism as mentioned in Ref. [2]. The thermal energy barriers are evaluated at three different values of temperature namely, $25 ^{\circ}\mathrm {C}($ room temperature), $100 ^{\circ}\mathrm {C}($ operational temperature) and $260 ^{\circ}\mathrm {C}($ solder reflow temperature). The required values, saturation magnetization (Ms), uniaxial anisotropy (Ks) and exchange constant (Aex) are used as measured in the GLOBALFOUNDRIES hardware [4]. Further, their temperature dependence is computed using Kinetic Monte Carlo simulations. The calculated thermal energy barriers, with varying MTJ diameters, are plotted in Figure 2 a). The MTJ diameters are varied between 5 – 60 nm which essentially encompasses 7, 10, 14 and 22nm CMOS technology nodes. The blue, red and green curves represent the data obtained at temperatures of 25, 100 and $260 ^{\circ}\mathrm {C}$, respectively. We observe that the lowest thermal barrier of approximately 30 KT can be achieved at 15 nm diameter for the highest solder reflow temperature. This implies that the MTJ diameter can be scaled down to 15 nm without compromising the thermal stability as required by 0.1 FIT's for 21 days. However, the energy barriers are drastically reduced below 15 nm diameter. Figure 2b) shows the switching efficiency figure of merit for p-MTJs, which is defined as the ratio of the energy barrier and switching current. Here, the critical switching current is calculated using the macrospin model described in Ref. [5]. From this plot it can be observed that the switching efficiency of MTJ saturates at smaller diameters. These diameter values, at which the switching efficiency saturates, reduces with increasing temperatures. In summary, we presented a comprehensive benchmarking of STT-MRAM for cache applications. The data shows that STT-MRAM is indeed scalable and can be integrated with advanced CMOS nodes. Our results clearly show that the thermal stability requirements for L3-cache can be met at even smaller MTJ diameters. Finally, the critical diameter at which the switching efficiency saturates is also dependent on temperature.