Low voltage low power full adder for baseband circuits in wireless systems

A low voltage low power 1-bit full adder is proposed for digital baseband in wireless systems. The full adder adopts stacked NMOS transmission gates and inverters as the building block. Leakage power is well controlled and desirable power-delay product (PDP) is achieved. When the adder is implemented in TSMC 65 nm low-VT process, the leakage power is only 1.43 nW at 0.4 V power supply, while PDP is 4.84 nW*ns. Good noise margin is also obtained at low voltages.