A 2-to-10 GHz 1.4-mW 50% Duty-Cycle Corrector in 40-nm CMOS Process (Invited Paper)

This work presents a 50% duty-cycle corrector (DCC) with high frequency, wide frequency range and low power consumption. A low-pass filter with programmable bandwidth is added not only to reduce the ripple of the control voltage at different frequencies but also to stabilize the DCC feedback loop over wide operation frequency range. A single-ended push-pull duty-cycle adjuster is adopted to achieve wide duty cycle adjusting range and low-power consumption. This DCC is designed in 40-nm CMOS process with 1-V supply. Post-layout simulation results show that it can correct the duty cycle of the output clock to $50 \pm 0.5$ % with the input duty cycle range from 20% to 80% and the operation frequency range from 2 to 10 GHz. The maximum power consumption is 1.4 mW.