Predictive Model for Extreme Electromagnetic Compatibility on CMOS Inverters

This paper presents an analytical model to predict and characterize the impact of Extreme Electromagnetic Interference (EEMI) on Voltage Transfer Characteristic (VTC) of CMOS inverters as a function of device scale. The predictive model determines the slope of VTC based on only a few primitive technology parameters. The developed analytical model is successfully compared against measurement data from a CMOS inverter fabricated using TSMC's 350nm standard CMOS process. Based on the predictive model the tolerance to EEMI injected power in a CMOS inverter reduces by technology scaling, starting from 14dBm at 350nm down to 3.5dBm at 65nm technology node.