A 0.6-V Supply Two-Step Time-to-Digital Converter Using Dynamic Threshold Technology

A two-step time-to-digital converter (TDC) that achieves linear, high-speed time quantization, high-resolution under a 0.6-V supply is proposed in this paper. In order to work in low-voltage supply, dynamic threshold technology is used. The TDC mainly consists of two vernier delay-line TDCs and an array of SR-latch-based time amplifiers to achieve high resolution. This TDC is designed in a 65-nm CMOS technology. Simulation results of this TDC show that the minimum time resolution is 2.5ps while only consuming 0.5mW. The differential nonlinearity (DNL) of this proposed TDC is 0.9LSB and the integral nonlinearity (INL) is 2.3LSB.