Simulation and Low Cost Process Development of Thin Wafer Level TSV Last Integration Scheme for RF Applications

The use of 3D/TSV technology enables enhanced packaging roadmaps for a wide range of electronic products. Within the 3D/TSV application space, a variety of TSV structures and dimensions are available for use depending on the product needs (i.e. solid and annular TSV shapes). As RF modules continue to gain in functionality by integrating more devices into the package, the benefits of integrating 3D/TSV technology into the module are becoming more apparent. Not only can overall module sizes be reduced through die stacking, but power and electrical performance are also improved by reducing die-to-die wiring lengths. In this study, electrical simulations were completed to quantify TSV performance up to 100GHz frequency. In addition, a series of mechanical stress simulations were completed to understand impacts of the TSV structures on the base Si substrate. Based on the simulation results, a cylindrical TSV Last process was developed using an advanced RF technology node that includes capabilities for both isolated and grounded TSV applications. The utilization of a unique dry film process has resulted in a low cost, high reliability integration flow. In this work, we demonstrated the TSV process without dry film polymer liner. We are currently developing the vacuum lamination process for dry film polymer liner which will be reported in our future work. In addition, we reported the polymer filling process for TSV by using dry film vacuum lamination process. Further process enhancements are planned to complete the enablement of this process for 3D RF products.