Thermally Aided Nonvolatile Memory Using $\pmb{\mathrm{ReS}_{2}}$ Transistors

Recently two-dimensional (2D) materials have attracted significant research interest for memory applications. Monolayer (MoL) as well as multilayer (ML) MoS
₂
have been used for demonstrating thermally assisted non-volatile memories (NVM) [5, 6]. With increasing packing density of FETs on a single wafer, high performance ICs can reach an operating temperature closer to 370-530 K range [3] making it important to understand and exploit the behavioural changes in these materials at higher temperatures (HT). Thermally assisted NVM is one such application where locally generated heat is exploited to aid the switching between RESET (RST/STATE 0) and WRITE (WR/STATE 1) states [4]. In this study thermally varying hysteretic gate operation in ML MoS
₂
and for the first time in ML ReS
₂
is studied and compared for NVM application. Due to lack of interlayer coupling ReS
₂
behaves as decoupled MoLs making it a direct band gap material (E
_G
-1.5 eV) for both ML and MoL [2] and hence is of interest for optoelectronic applications in MoL as well as ML form. We demonstrate clockwise (CW) hysteresis at lower temperatures (LT) and anticlockwise (ACW) plus step like conductance crossover (STC) hysteresis at 373 K & 400 K for ML ReS
₂
and MoS
₂
respectively. Similar hysteresis behaviour has been previously reported for MoL MoS
₂
only at a very high operating temperature of 500 K [5]. STC hysteresis provides an edge over CW hysteresis at HT in terms of lower operating voltages (V
_p-p
), larger RST to WR window defined here as ΔV
_th
/V
_p-p
(where ΔV
_th
is the hysteresis width) and larger READ (RD) window. These parameters for previous NVM reports are mentioned in Table 1 and compared with this work. ML ReS
₂
operates at much lower temperatures, lower Vp-p and has larger WR to RST and RD windows as compared to MoS
₂
.