An Incremental Algorithm for Soft Error Rate Estimation of Combinational Circuits

With the scaling of CMOS transistor dimensions, soft errors in combinational logic circuits are emerging as a significant reliability concern in nano-scale digital systems design. Hence, fast and efficient approaches to estimate the soft error rate (SER) of combinational circuits have become significantly important. SER is a crucial diagnostic metric which provides valuable information to guide SER optimization and reliability-driven logic synthesis. Existing works for SER analysis in the literature, however, computes this metric in a non-incremental manner, that is, after one or more changes in a previously timed circuit, it is required to recompute SER from scratch, which is obviously undesirable for optimizing large circuits. In this paper, an incremental technique is presented to estimate the SER of combinational circuits. An accurate model is proposed for SER estimation by considering all three masking mechanisms (namely, logical, electrical, and timing). The proposed incremental re-estimation SER algorithm is based on the information provided by the primary SER calculation. A set of rules, based on the topological locations of logic gates in the circuit graph, is introduced to identify the portion of the design for which the gates SER are affected, and quickly computes the new SER values. Experimental results on ISCAS'89 benchmarks show that, on average, 10 times speedup is achieved during SER re-estimations without sacrificing accuracy.