Die Edge Crack Propagation Modeling for Risk Assessment of Advanced Technology Nodes

Cracks at the die edge induced by dicing can grow due to chip-package interaction (CPI) and thermal cycling experienced in service. The semiconductor industry has been making major efforts to prevent die edge cracks from propagating into the active area of a chip. Patterned metal structures are commonly introduced around the perimeter to play a role as crackstop by increasing the fracture resistance near the die edge. In advance technology nodes, while the introduction of ultra low-k (ULK) materials reduces the RC delay, it also adds to the CPI challenge due to its weaker mechanical strength and fracture resistance. Die edge cracking risk is thus still a major reliability concern. In this report, a structured methodology that can address the die cracking reliability challenges is presented. Experimentally, we found that the effectiveness of crackstop structures for arresting dicing crack propagation depends on the following aspects: (1) BEOL stack, (2) crack stop design, (3) dicing location, (4) substrate. In this paper, multilevel finite element method (FEM) simulations are conducted to provide fundamental understanding of the failure mechanism. Cohesive zone modeling (CZM) is implemented in the last level of submodel to simulate the dicing crack propagation. A fracture mechanics-based methodology is implemented to calculate the crack driving force (energy release rate) and identify the weakest layer in the BEOL stack. The effect of BEOL stacks, packaging stress, and crackstop location are investigated thoroughly to study key drivers of the various die edge cracking behaviors observed experimentally. We demonstrate that the methodology presented herein can be used to investigate die edge cracking risks for future advanced technology nodes.