Heterogeneous Multi-die Stitching: Technology Demonstration and Design Considerations

In this paper, a Heterogeneous Interconnect Stitching Technology (HIST) is reported. In the proposed approach, stitch-chips, which may be active or passive chips, are placed between the package substrate and concatenated 'anchor chips'. Fine-pitch Compressible MicroInterconnects (CMIs) are used to provide low-loss and robust interconnection between the anchor chips and the stitch-chips. The CMIs are also used to compensate for any package non-planarity and stitch-chip thickness variations, as one anchor chip may interface to multiple different stitch-chips at each of its edges. Electrical measurements of the assembled chips are reported and demonstrate robust interconnection. Integrated circuits in the HIST platform are thermally evaluated to investigate thermal challenges and opportunities for such multi-die packages. Impact of different parameters, including die-spacing, stitch-chip splitting, and die-thickness mismatch, for example, on the thermal profile are evaluated. Moreover, power delivery network analysis is performed for the HIST platform with focus primarily on the IR-drop as a function of the overlap area between the anchor dice and the stitch-chips.