fT Enhancement of CMOS Transistor Using Isolated Polysilicon Gates

This paper presents a layout method using isolated polysilicon gates to boost the current gain performance of CMOS transistor while preserving symmetrical contact geometry for mismatch consideration and enable flexibility in gate routing. It demonstrated less gate capacitances than conventional comb type layout due to reduction in polysilicon area. Consequently, 12GHz improvement in maximum transit frequency, f
T
is recorded even for optimization at single gate level. Further, variants of isolated gate layouts are introduced to allow flexibility in optimizing the transistor gate parasitics. They are found to have negligible impact on gate resistance for the same double gate contact style. The advantages described are realized without compromising maximum power gain as demonstrated experimentally.