Implementation of leakage reduction techniques in finfet based 3T DRAM based at 45 nm technology

In this paper we have compared the average power, leakage power, leakage current and leakage voltage of a 3-T DRAM circuit. To compare the performance of 3T DRAM we use the FinFET approach and SVL technique. This is the type of gate structure which helps to reduce leakage current amount and overcomes some type other short-channel effects and enhanced electrical control over the channel conduction. SVL is the technique which used to decrease leakage during both the stand-by mode and active mode. DRAM is used in several processors for data memory purpose. In modern day personal computers DRAM is used as the main memory. The Off-state leakage current is the main reason behind power dissipation in DRAM structures. The basic advantage of using DRAM is simplicity in its structure.