Improvement of package warpage through substrate and EMC optimization

Package warpage significantly affects the yield and reliability of package assemblies such as POP and board level surface mount. As the size of silicon die is fixed and its thickness is usually thinned down to the minimum, the only remaining variables to control the package warpage are the substrate and EMC. Therefore, the co-optimization of the substrate and EMC is critical to improve the package warpage behavior throughout the assembly temperature profile for the best yield and reliability. Using simple bilayer structured specimens composed of various substrates and EMC's, we measure the warpage which is dependent on their CTE, modulus, and shrinkage. Then, we verify the mechanism of package warpage by comparing measured data with simulation results. Finally, we predict the warpage of real package structure using the verified warpage mechanism of simple cases. We explain the importance of shrinkage in solving room temperature package warpage. This systematic analysis and simulation approach improves the package warpage with minimal experimental iterations.