Patterning technology options for future scaling

Self-aligned multiple patterning technique has enabled the further down scaling through 193 immersion lithography extension [1-4]. In particular, focus on the logic device scaling, we have finished the verification of patterning technology of up to 10nm node [5-6], we will discuss about some patterning technologies that are required to 7nm node. For critical layers in FinFET devices that presume a 1D cell design, there is also a need not just for the scaling of grating patterns but also for pattern cutting process. In 7nm node, cutting number increase in metal or fin layer, and also pattern splitting of contact or via is complicated, so both cost reduction and process controllability including EPE are strongly required. This paper presents the possibility of immersion-based multiple patterning techniques and EUV lithography applicability for up to 7nm node.