Integrated solder bump electromigration test chip and coupon cards for the characterization of Pb-free SAC solders under stress

As silicon power integrated circuits continue to shrink in scale to enable inclusion in mobile devices, the use of wafer level chip scale packages (WLCSPs) is becoming more common. Power devices are typically used in applications where a high current device relies on multiple solder connections to pass current in applications such as battery chargers and USB input switches where power transmission is important. In such applications, the traditional failure mechanism of crack propagation due to drop/shock or temperature cycling of the solder bumps can be overshadowed by electromigration failures in the Sn alloy, as relatively low current densities are required to cause voiding. To characterize the electromigration behavior of Pb-free solder bumps used in wafer level chip scale packages (WLCSPs), a combined test chip / PCB card has been designed for flexibility of test. This test vehicle combines the JEDEC recommended single ball and daisy chain type test structures on a single chip, along with a serpentine resistor specifically for characterizing the temperature of the Under-Bump Metallization (UBM) and die surface. This added resistor not only aides in the careful characterization of bump temperature near the liquidus point of the solder alloy, but also enables an asymmetrical thermal migration tests where die temperature is held higher than ambient temperature. Imaging of failed solder bumps after high stress EM testing linking lifetime data and rapid changes in the solder bump test vehicle will provide direction for high-reliability solder bump design and materials.