Performance analysis of a low power high speed full adder

The paper presents a performance analysis of a low power high speed full adder which shows that how power dissipation become low using the different technologies in a Cadence Virtuoso tool. The design was first implemented in 250nm technology for 16 CMOS transistor further it was implemented in various other technologies. In paper the first part deals with the implementation and then the comparison of 16 transistors in all technologies like 250nm, 180nm, 90nm, 45nm, 32nm, 22nm and 16nm. The next part deals with the implementation of full adder circuit by reduce the number of transistors from 16 to 6 CMOS transistor. We observe that the power dissipation become very low using 6 transistors in 250nm technology as compared with the 16 transistors in various other technologies.