The development of a true-type logarithmic amplifier on capacitor dividers for ADC

The increase of the ADC bit capacity is possible by involving the compression of the input signal according to the logarithmic law, while maintaining the phase of the signal. Theoretical calculations and computer simulation of the ADC coupled with the logarithmic amplifier demonstrate the significant improvement of the operating parameters of the circuit, the increase in dynamic range and decrease in the spread of the relative conversion error. The paper presents a logarithmic amplifier (LA) with 3.5 GHz bandwidth, 30 dB gain and 70 dB dynamic range. Current consumption is 90 mA and supply voltage 5 V. The mathematical description of the proposed inclusion method, as well as a graphical representation of the obtained parameters are presented. Methods for calculating the dynamic range are described and a comparison between two variants is made. Schematic modeling of the proposed method is carried out and the results are presented.