Tree-based algorithm for design space exploration and mapping application onto heterogeneous platforms

Application task mapping onto a given heterogeneous processors has been known as one of the most significant problems in system level design of embedded systems. The huge number of mapping configurations as well as the complexity of evaluating a mapping, makes the task of finding optimal solutions a really time-consuming task. This paper proposes a novel tree-based exploration algorithm to solve the mapping problem. The algorithm prunes the design space such that it can be explored in less time while it still includes desirable points. The proposed Algorithm perform exploration in multilevel and in each level uses Genetic Algorithm for searching among mapping configuration. Simulation results reveal that multi-level explorations lead to find near-optimal mapping efficiently, with more than 91% accuracy in less time.