A hardware design method for Canonical Huffman Code

With the development of multimedia network and computer technology, Canonical Huffman Code hybrid compression algorithm has been widely used, improving image processing technology rapidly. As an important subset of the Huffman algorithm, Canonical Huffman Code solves many shortcomings of the Huffman algorithm. The Canonical Huffman Code can be coded based on the coded bit length. So that the output of the code table is greatly reduced, and the coding process no longer needs a binary tree structure. At the same time, memory footprint is also reduced significantly because the speed of coding is increasing. In this paper, we use the optimized bubble sort algorithm and Canonical Huffman Code algorithm. In the case of using a small amount of FPGA hardware resources and ensuring a minimum coding variance, a comparable clock frequency can be made.