Huffman coding method based on parallel implementation of FPGA

With the rapid development of science and technology, the requirement of data compression speed is getting higher and higher. In recent years, software implementation of image compression technology in the general-purpose computer or DSP chip cannot meet the real-time processing speed requirements. Field Programmable Gate Array (FPGA) is a new type of digital circuit. Each logic gate in the FPGA chip performs some logical operation at the same time every clock cycle. Obviously, FPGA is essentially a large-scale parallel hardware device. In this paper, the parallel processing features of FPGA and parallel Huffman coding are utilized. Different from the traditional sorting algorithm, this paper uses the parallel characteristics of FPGA, using parallel full comparison algorithm. By using this algorithm, it will take only one clock and a small number of clock cycles to get all the data sorted. And the FPGA implementation exports the results through a three-stage pipeline.