Low power high speed 1-bit full adder circuit design in DSM technology

In today's high-speed communication world the usage of electronics portable devices is increasing day by day, as the devices are portable and compact it has to satisfy the need of low power dissipation and minimum area requirement along with the high speed. A one bit full adder cell is one of the most frequently used digital circuit component in arithmetic logic unit (ALU) and it is the essential functional unit of all computational circuit. Till now many improvement has been done in this area to refine the architecture and performance of full adder circuit design. This paper mainly focus on two novel 1-bit full adder cells which is designed on 32 nm CMOS technology with different operating frequencies at 1 v supply voltage. The design of two novel 1-bit full adder cells along with three existing adder cells are incorporate in this paper and their complete comparison and verification has been done in terms of power dissipation, delay and power delay product (PDP) at different operating frequencies by using HSPICE tool. It is found that the existing Static Energy Recovery Full (SERF) adder and Gate Diffusion Input (GDI) full adder provides poor performance when compared with proposed adder cell and also its equivalent layout has been generated to calculate the area of existing and proposed adder cell by using Microwind 3.5 tool. From the simulation result it is observed that the first proposed adder circuit using XOR module has achieved maximum saving of PDP 46.71% & 96.61% when compared to existing SERF and GDI adder cells respectively. The second proposed circuit using XNOR module has achieved maximum saving of PDP 74.59% & 98.38% when compared to existing SERF and GDI 1-bit adder cells respectively.