Efficient decoupling and filtering for multiple loads and voltage domains with composite capacitors

Placement of discrete capacitors per unit area is restricted by solder resist opening (SRO) spacing rule. In addition to processor die size and bump pitch reduction over generations, number of voltage rail increase due to power management requirements have led to insufficient independent capacitors allowed for each load for self and cross-noise mitigations [1-4]. This paper presents a new capacitor technology to eliminate need of SRO spacing for performance and/or area benefits. Up to 30% impedance reduction and 38% increase in total capacitance per unit area is shown to be feasible. In addition, integration of isolation filter for cross-noise mitigations is described. Design guidelines are derived to decide integrated negative coupling factor for optimized self and cross-noise reduction.