Modeling and characterization of polymer-embedded through-silicon vias (TSVs) in 3-D integrated circuits

The polymer-embedded TSVs have advantages of high isolation and easy fabrication of re-distribution layers. In this work, the electrical model is established for analyzing characterization of the through-silicon vias (TSVs) array in polymer well. The parasitic parameters are extracted based on physical parameters. Then the characteristics of differential TSVs are easily obtained by means of the single-ended-TSV S-parameters. Additionally, comparisons and analysis of S-parameters are made between the polymer-embedded TSVs and the insulation-liner TSVs available. The differential insertion loss of TSVs in polymer well is far less than the others.