Integrated dual SPE processes with low contact resistivity for future CMOS technologies

In this study, a manufacturable CMOS dual solid phase epitaxy (SPE) process with pc < 2.2×10
⁻⁹
Q-cm
²
on both NFET and PFET is demonstrated on the hardware with 7nm ground rule. Contact resistivity reduction strategies of both the conventional approach of high in-situ doped epi and the novel SPE processes are systematically studied on device and ring oscillator (RO) level. Clear improvement in the RO delay is accomplished by the novel dual SPE process on the CMOS flow. Stronger performance benefit is demonstrated with smaller contact sizes towards future CMOS technology nodes.