Research on test scheduling of 3D NoC based the strategy of bandwidth division multiplexing and multi-clock

To improve the testing efficiency of IP core in 3-dimensional network-on-chip (3D NoC), research on test scheduling of 3D NoC under multi-constraint is conducted. In this paper, we use the strategy of dynamic bandwidth division multiplexing to increase the utilization of 3D NoC. The strategy of multi-clock is used to determine the clock frequency of each IP core according to the ratio of power consumption and test time to shorten its test time. The improved particle swarm optimization (PSO) algorithm is used to find the optimal solution under the dual constraints of power consumption and bandwidth, which combined with the characteristics of 3D NoC. The location and order of transmission of the IP core's test data are viewed as two variables to optimize. The optimal speed and accuracy of the algorithm are advanced by adding the Explosion Operator (EO) and Specific Introductory Formula (SIF) in early phase, and the strategy of local optimal monitoring is added in the later phase. The circuit in international standard test set ITC'02 is used as the experimental object. The experiment results show that the work in this paper can shorten the test time and improve the utilization of on-chip resources effectively.