Copper pillar plating systems

This present paper deals with the ever-more stringent requirements of to-date Interconnect Technologies (ICT) from die through final assembly in particular as far as digital and analog high frequencies, undistorted signal propagation and efficient heat propagation are concerned. From wafer level packaging to the finished Printed Circuit Board copper pillars, solid copper posts continue to play a vital role in coping with high speed/frequency and high wattage of sub and final assemblies. Commonly used packaging concepts comprising wafer level plating, through-silicon-vias (TSV), redistribution layer design (RDL), intermediate pillars, macro bumps and copper filled through holes in the final circuitry are being roughly sketched by an overlook of the extremely different pillar geometries within each packaging level posing individual challenges on the copper plating chemistry and process. Practical aspects namely dialing in the chemistry additives and process windows to match the requirements will be discussed, the ongoing R&D work targeted for current and future requirements to be presented. This paper concludes with a plating process on high copper pillar.