Power source consideration for 56Gbps I/O interface

In our previous study, we argued that stabilization of power source voltage by optimizing a chip wiring feature was essential to achieving high performance transmission for over 40 Gbps I/O on an interface circuit. This region frequency transmission approach is fairly important to solve communication bottleneck. We will examine power supply wiring for more high frequency (over 40 Gbps) which is significant to maintain signal integrity from the viewpoint of an eye diagram and driver device metrics. This focuses a inverter CMOS driver and a differential 40mm-long transmission line using a Synopsys HSPICE simulator with a pseudorandom binary sequence (PRBS32) input signal and simulation models of TSMC 65nm IP's (Intellectual Property), Arizona State University Predictive Technology 32nm and FinFET. In the previous study, simulated results show that configuration of the power source wiring should be carefully considered. A parallel plate structure provides good eye diagrams at 20Gbps in the TSMC 65nm IP's compared to the Loop structure. VDD fluctuation is also fairly low for the parallel plate structure circuit and very high for the Loop Structure circuit. In this study, we focus on other device metrics and higher frequency for 56Gbps region.