A novel Κ convention logic (NCL) gates architecture based on basic gates

Digital circuit design may demand critical requirements, such as power consumption, robustness, performance, etc., while being implemented in VLSI (Very Large Scale Integration). The asynchronous paradigm presents interesting features that serve as an alternative to these critical requirements. An important class of the asynchronous paradigm is the one called QDI (Quasi Delay Insensitive) circuits that can also be used for critical requirements design. QDI circuits are interesting for these applications because they are robust to certain kinds of faults, to noise and to temperature and supply voltage variations, having also low electromagnetic emissions. An interesting style of QDI circuits is the NCL (NULL Convention Logic) circuits because they accept conventional Boolean functions and can achieve great optimization. This paper presents an architecture based on basic QDI gates for the synthesis of NCL gates focusing on VLSI that uses only standard libraries and FPGA (Field Programmable Gate Array).