Development of the asynchronous readout ASIC for GEM detectors

Currently the multichannel readout chip for GEM detectors with an asynchronous architecture is being developed. The readout channel includes a preamplifier with fast and slow CR-RC shapers, discriminator with a differential threshold setup circuit, a 6 bit SAR ADC (40 Msps rate, 1.5 mW power consumption), digital peak detector and block of the time stamp registration. The digital peak detector has a feature, preventing the false peak detection. The final chip version is considered to be compatible with the GBTx data processing board. Thus, the control data, clock and output data are supplied through SLVS transmitter and receiver. The slow and fast channels have 1500 el and 2000 el ENC accordingly at a 50 pF detector capacitance. Power consumption is 10 mW/channel. The paper describes the last results in building blocks schematic and layout design, test benches and the results of the lab study.