An active analog delay using delay reference loop

With the development of high-speed mixed-signal circuits, signal timing for the overall system have a crucial impact. Analog delay circuits are widely used in high-speed circuits. In this paper, a compact gm-c active delay is used, while a delay reference loop is used to adjust the delay time. The design and simulation are implemented by 0.13 um SiGe BiCMOS. The chip occupies 0.40 mm
²
die area, consuming a power of 227 mW from 2.5 V power supply. Post simulation results demonstrate that single delay unit delays from 3.60 ps to 4.93 ps with 27% adjustment range in frequency (1-20 GHz).