Three-dimension space vector modulation for three-level four-leg inverters with DC-link capacitor voltage balancing and switching loss minimization

Due to the trend of decentralized generation (DG) residing in low voltage distribution network, more inverters are connected to the grid in three-phase four-wire systems under asymmetrical condition. This paper presents an algorithm to balance DC-link capacitor voltages and minimize switching loss of three-level four-leg inverters which is suitable for asymmetrical condition. The algorithm is based on three-dimension space vector modulation (3D-SVM) in natural coordinates. The algorithm balances DC-link capacitor voltages by the selection of redundant standard vectors. Switching sequences are selected to minimize switching loss. Simulation results show that the method is able to balance DC-link capacitor voltages and reduce middle point voltage ripple.