A Comprehensive Study on Stress and Warpage by Design, Simulation and Fabrication of RDL-First Panel Level Fan-Out Technology for Advanced Package

Rapid development of semiconductor technology and multi-function demands of end products has driven IC foundry industry toward 7nm node process, and even next generation of 5nm. The I/O pitch of chip is reduced accordingly but the build-up layer of IC carrier is still too large to fit interconnects. In order to overcome the gap of I/O pitch between IC chip and carrier, the interposer technology has been considered as a solution to resolve the issue. However, the cost of silicon interposer is too high, and the glass interposer lacks the associated infrastructure and is difficult to be handled, which makes a technology drawback for market applications. Alternatively, fan-out wafer/panel level package technology is getting more attractions for advanced package recently because of its features of low profile, small form factor, and high bandwidth with fine line re-distribution layer (RDL) routability. There are lots of literatures addressing about the residual stress and warpage mostly on wafer level fan-out technology, especially for chip-first technology scheme. However, comprehensive study on the panel level fan-out is not mature yet. This paper investigates fundamental factors that impact the residual stress and warpage level of panel level fan-out package, such as metal layer counts, thickness of dielectric and metal layer, coefficient of thermal expansion (CTE) and Young's modulus of dielectric and molding compound, molding gap and molding process temperature, etc. In this study, a RDL-first (chip-last) fan-out panel level structure of three metal layers on releasing film molded with epoxy compound was established as a simulation model by means of finite element analysis software. The simulation results provide a guideline of design rules for fabricating multi-layer RDL panel level fan-out package and making the minimum residual stress while chip assembly. Fabrication of three-layer dielectric panel level fan-out, where 370mmx470mm panel size is applied, is also demonstrated to compare with the simulation results.