Clock Tree Synthesis and optimization in BES1300 IC Smart Card

This paper provides several methods by using Synopsys IC Compiler (ICC) to optimize Clock Tree Synthesis (CTS), reasonable floorplan, parameter constraint, manual specification, Engineering Change Order (ECO) included. An IC smartcard named BES1300 using 0.18μm EFLASH 2P4M technology is applied to verify the propose methods. Optimizing timing manually is mainly described. Testing results show that hold violation improves 34% and area reduces 9%. The validity of methods is proved by the tape out result.