A V-band 40 nm CMOS phase locked loop with mutual injection locking technique

This paper presents a V-band phase-locked loop (PLL) that employs zero blind zone phase frequency detector (PFD) and mutual injection-locking voltage controlled oscillator (VCO) to improve signal quality performance. This architecture is fabricated in 40-nm CMOS process with a die area of 0.7 mm
²
. The silicon results demonstrate an excellent in-band phase noise of -90 dBc/Hz at 500 kHz offset with 2.5 MHz bandwidth. The PLL draws 40.8 mA current (including output buffer) from a 1.2 V power supply while operating at 60.8 GHz.