A die selection and matching method for yield enhancement of 3D-stacked memories

Three-dimensional (3-D) memories using through-silicon-vias (TSVs) as vertical buses across memory layers have been regarded as a promising solution to fulfill the ever-increasing demand of memory capacity. However, the yield improvement issue is an important challenge for memory manufacturing. For 3-D memories, redundancy sharing between dies using TSVs is an effective strategy for the yield enhancement. Since different dies have different fault bitmaps resulting in various repair solutions, the strategy of die selection and matching has a great influence on the yield. In this paper, a new die selection and matching method is proposed to enhance the yield of 3D-stacked memories. Experimental results show that the proposed method has a 16.6% and 0.9% improvement on average yield compared with KGDs method and Die-die matching scheme respectively.